It is known as the so-called dark silicon problem that all the transistors cannot be caused to operate simultaneously because of the balance with power consumption.
Due to the abovementioned problem, there is a case where an electronic circuit needs limitation of the operation thereof as necessary. That is to say, because there is a fear that simultaneous operation of all the circuits results in excessive power consumption and malfunction, there is a case where it is required to limit the operation of the circuits as necessary and thereby prevent excessive power consumption.
As one of the techniques for preventing such an operation of the circuits, Patent Document 1 is known, for example. Patent Document 1 discloses a processor which includes a power accumulation part accumulating power information about power consumed during issuance of an instruction, a comparison part comparing the accumulated power information with a given threshold, and a control part blocking another instruction from being issued. According to Patent Document 1, in a case where the accumulated power information exceeds the threshold, the control part blocks another instruction from being issued.
Further, a technique for limiting power consumption in a multi-core system is shown in Patent Document 2, for example. Patent Document 2 discloses a multi-core system having a processing time estimation part and a task allocation pattern setting part. According to Patent Document 2, the task allocation pattern setting part sets a task allocation pattern so that the size of the cache used by tasks is the minimum and power consumption is the minimum within a range that a task processing time estimated by the processing time estimation part satisfies a real-time constraint according to deadline information. According to Patent Document 2, the abovementioned configuration enables allocation of the cache to more tasks, and consequently, the frequency of occurrence of cache rewrite can be reduced even when task switching occurs.    Patent Document 1: Japanese Unexamined Patent Application Publication No. JP-A 2013-518346    Patent Document 2: Japanese Patent No. 5585651
However, use of the techniques as disclosed in Patent Documents 1 and 2 may cause a case where electric power usable for an LSI cannot be used up. As a result, there is a case where limitation such as decrease of the issuance rate is put and the performance is diminished though the LSI can still consume electric power.
As stated above, a multi-core processor has a problem that it is difficult to control power consumption for each processor core without diminishing the performance of the whole.